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sda1902's avatar
sda1902
Icon for New Contributor rankNew Contributor
1 year ago

SFL problem

Hi ! In my project, I planned to use SFL to access the configuration flash, which was planned to contain not only the configuration, but also the data. Problem: The SFL project loads into the FPG...
Configuration
FakhrulA_altera's avatar
FakhrulA_altera
Icon for Regular Contributor rankRegular Contributor
1 year ago

Hi sda1902,


My apologies I may have overlooked this post. Here a few item you may need to check:

  1. Instantiate SFL IP Core Correctly:
  • Ensure proper instantiation in the top-level design to connect JTAG and ASMI hard logic.
  1. Set Configuration Signals:
  • Set noe_in to 0 to enable the SFL IP core. If not accessing ASMI externally, tie this signal to GND.
  1. JTAG to AS Bridge:
  • Load the SFL image to bridge JTAG to the ASMI interface, crucial for programming via JTAG-ASMI.
  1. Shared ASMI Interface:
  • Enable Share ASMI interface if sharing the ASMI interface in your design.
  1. Enhanced Mode SFL:
  • Ensure Use enhanced mode SFL is appropriately set. For Cyclone V and Arria V devices, this parameter must be enabled.
  1. Programming Flow:
  • After programming, reconfigure the FPGA by cycling the nConfig pin.


For further details, please refer to the provided document - AN 370: Using the Intel FPGA Serial Flash Loader.


Regards,

Fakhrul