Forum Discussion
Altera_Forum
Honored Contributor
Honored ContributorSetup timing violation
Should I just split the combinatorial logic at line 15 of the following verilog module or https://github.com/promach/internal_logic_analyzer/blob/master/rtl/check_data.v#l15 across several registers ...
Altera_ForumHonored Contributor
Honored ContributorOK.
By the way, I found out what went wrong with my setup timing violation. It is due to my mistake in timing constraint xdc file. My system clock is 1Ghz
