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Altera_Forum
Honored Contributor
Honored ContributorSetup timing violation
Should I just split the combinatorial logic at line 15 of the following verilog module or https://github.com/promach/internal_logic_analyzer/blob/master/rtl/check_data.v#l15 across several registers ...
Altera_ForumHonored Contributor
Honored ContributorYour screen cap is too small to see, but you should certainly perform some of those calculations and comparisons outside of the always block in their own assign statements.
So you could say assign data_out_calc = data_out + `MEMORY_SIZE + `ALIGNMENT_DELAY; and do a check of just data_out_calc in the if statement. You could also do something similar for the righthand side of the if statement comparison check.
