Hi @sstrell,
thanks for the reply, due to the maintenance of the forums I wasn't able to post earlier.
Yes the $pll_pin0 is the output clock pin of the PLL. One strange thing is that in Quartus I configure the PLL to have two clock outputs, on for the system clock and one for the sdram clock (in order to have smaller fan-out) and both of them are configured to be the same frequency (60 MHz) and have the same phase. But when I apply the "derive clocks pll" in my SDC file, Quartus uses for both the same PLL clock output pin to do timing analysis. I suppose this doesn't make any difference, for the reasons I mentioned above (same frequency, same phase).
For the moment I am not applying a false path on the generated clock but I am not sure if I should indeed false path it or not. The clock used to generate this clock, before reaching the output port "sdram_clk_pad_o", it is used also to clock the Controller of the SDRAM. Actually the controller of the SDRAM gets both the system clock and the clock destined for the SDRAM. What do you believe on this? Should a false path on the generated clock affect it?
Also I did some search the last couple of days and came up with the following on how to constraint my Source Synchronous interface with the SDRAM:
set clk_sdram_period 16.6667
#**************************************************************
# SDRAM Constraints
#**************************************************************
## SDRAM timing parameters from Datasheet
##
## From Datasheet: DATA, ADDRESS, CKE, CS, RAS, CAS, WE, DQM all have
## the same setup/hold time
##
## DATA tco(min) = tOH, tco(max) = tAC
set sdram_tsu 1.5
set sdram_th 0.8
set sdram_tco_min 2.7
set sdram_tco_max 5.4
# FPGA timing constraints
set sdram_input_delay_min $sdram_th
set sdram_input_delay_max [expr {$clk_sdram_period - $sdram_tsu}]
#set sdram_input_delay_max [expr {-$sdram_tsu}]
set sdram_output_delay_min $sdram_tco_min
set sdram_output_delay_max $sdram_tco_max
# FPGA outputs to SDRAM
set fpga2SDRAM_outputs [get_ports {
sdram_a_pad_o[*]
sdram_ba_pad_o[*]
sdram_cas_pad_o
sdram_cke_pad_o
sdram_cs_n_pad_o
sdram_dq_pad_io[*]
sdram_dqm_pad_o[*]
sdram_ras_pad_o
sdram_we_pad_o
}]
# FPGA inputs from SDRAM
set SDRAM2fpga_outputs [get_ports {
sdram_dq_pad_io[*]
}]
# Set Output Delay
set_output_delay -clock clk_sdram -max $sdram_input_delay_max $fpga2SDRAM_outputs
set_output_delay -clock clk_sdram -min $sdram_input_delay_min $fpga2SDRAM_outputs
# Set Input Delay
set_input_delay -clock clk_sdram -max $sdram_output_delay_max $SDRAM2fpga_outputs
set_input_delay -clock clk_sdram -min $sdram_output_delay_min $SDRAM2fpga_outputs
The scheme for the clocking of the SDRAM is depicted in the page 21 of the attached pdf.
As you can see on the diagram the setup time for the outputs of the FPGA (inputs to SDRAM) is the tCMS, which is the sdram_tsu in my SDC. This is 1.5 ns and the clock of the SDRAM is 60 MHz (16.6667 ns period).
I am troubled on what I should use in the "set_output_delay -max" option:
A) the -$sdram_tsu which is -1.5ns
B) the {$clk_sdram_period - $sdram_tsu} which is 16.667 - 1.5 = 15.167ns
C) whichever of the above I use are the same constraint
Can you provide your help on this?
Thank you in advance on your response and time.
Kind regards,
anm
p.s. for my previous post if you download the pic and open it, it has a clear and high resolution since it is a screenshot from a 3840 × 2160 screen. If you open it through the forum, it tends to make it smaller in order to fit it.
Occasional Contributor
