Set-up and hold time of ALTDDIO megafunction module

Thanks FvM and Rysc for the response. I will go ahead with the design assuming that the timing is similar to other core registers. Unfortunately, in one of my implementations, I cannot use PLL mode of the ALTLVDS module, since there are far too many clocks from the external devices in my design. Hence I want to find the limits at which a non-PLL design can work.

Thanks again,

--Shantanu.

--- Quote Start ---

Setup and hold requirements are essentially the same for all core registers, not only DDIO. I don't see a particular core register timing specification with the Arria V handbooks I checked (there may be newer revisions). But the requirement is reflected in the sample window specification for LVDS IO and discussed in the respective handbook parts.

--- Quote End ---