Set-up and hold time of ALTDDIO megafunction module

For 1Gbps, you'll want to use the altlvds_rx megafunction instead of altddio. The altlvds is not just an I/O element, but the whole interface. It uses a dedicated LVDS clock tree to feed from the PLL to the I/O, which is much more tightly controlled since it only feeds the I/O. It also doesn't use the DDIO, and instead uses a single capture register clocked at the full data rate, so there is no rise-fall variation.

When using this structure, you will want to run Report RSKM in TimeQuest. Also look at how the Sampling Window is calculated. From a timing perspective, the only major thing you need to do is when creating the megafunction, is tell it the phase-relationship between rx_in and rx_inclock. It will then shift the clock into the middle of the data eye. Note that you can put set_input_delay constraints on the inputs, but they're barely used. TQ just takes calculates the max minus min values and uses that to calculate RSKM. For example, if the set_input_delay -max was 0.4ns and the -min was 0.1ns, then the difference is 0.3ns, so 0.3ns of your 1ns data window is used externally. As long as the Sampling Window is less than 0.7ns, it meets timing. It doesn't look at the individual values though, i.e. if your -max was 10.4ns and the -min was 10.1ns, you'd get the same analysis.

At 1Gbps, you might want to use Dynamic Phase Alignment(DPA). It's just another switch in the altlvds megafunction. With this, there is no timing analysis at all, as the altlvds block just oversamples your incoming data stream and automatically chooses the best sampling point.