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I realize that the only requirement on the input register is that its setup time should be less than the TCO max of the device and that its hold time must be less than the TCO min. However,
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The wording is not right as tCO is relative to launch edge while tSU or tH are relative to latch edge. But I get what you think. The early margin of invalid window must be further from tH point and late margin must be before tSU point.
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I have one final problem that I've run into.While trying to constrain the output side, (which too is at 27Mhz, I seem to have a rather strange result). Please view the attached diagrams. The setup time -minimum value is 0.5 ns.The hold time -minimum value is 0.5 ns, but the Hold Time is described wrt to the falling edge of the clock(Data at output gets latched on the rising edge of the clock).I tried to implement this constraint by setting the minimum output delay to (18.5ns + 0.5ns), but the constraints fail.I have seen you post elsewhere that the min delay should be set to -tH, but that seems to be the case when tS and tH are wrt to the same edge.
Is this the correct way to constraint what is given in the diagram?
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You are showing two clocks; clock and its inversion and then you state that it is relative to falling edge.
if your fpga launches on rising edge then you need to adjust figures or launch on falling edge to make life a bit easier or use falling_clock if available in command
to adjust the figures I will assume that with respect to rising edge of device tSU = 18.5 - 0.5 = 18 & tH = 18.5 + 0.5 = 19
Then comes the entry of sdc commands. I feel both are negative now as they are behind presumed rising latch edge (or could be made positive relative to next latch) but I am not sure and you need to see what the tool does and how it interprets your entries, look at results such as output registers tCO(frm datasheet) or io path waveforms.
Whether it fails timing or not is a different issue. The starting point is enter the constraints correctly.
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