set_input_delay And set_output_delay .SDC Constraints

you are right about the meaning of these commands. You inform timequest what offset is coming of data relative to its clock edge launch.

so you are directly describing what the diagram is implying.

Then you are sampling data on the opposite edge. The fitter seems unable to manage that. By mis-informing the tool that it is relative to rise edge it managed that. You must enter the figures relative to falling edge i.e. 10/25. Or if you wish modify them to become relative to rise edge by adding 37/2 = 28.5/(43.5-37) i.e. 6.5/28.5 and so min/max offset also reversed.

It is obvious that the tool is happier if your figures of 10/25 were relative to rise edge but they are not. so either you sample on falling edge at fpga or use pll to invert the clock so you sample it on rising edge. The tool will be aware of that and should pass