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Altera_Forum's avatar
Altera_Forum
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13 years ago

set D.F during reset

Is it possible to set signals to different value other then 0 during the reset time?

For instance:

"if reset='1' then

pwm_count <=12; -- integer, is it allow?

PWM_Hex_CMD_Sample <=x"7F"; --std_logic_vector, is it allow?

Default_Num <= '1'; -- std_logic, is it allow?

Positive_Edge <= '0';

Negative_Edge <= '0';

elsif clk'event and clk='1' then"

The target is Cyclone III, EP3C25F324.

Thanks,

Idan :rolleyes:

1 Reply

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    13 years ago

    --- Quote Start ---

    Is it possible to set signals to different value other then 0 during the reset time?

    --- Quote End ---

    Yes, you can set signals and registers to specified values at both power-on and on reset.

    Eg., power-on signal value: 

    
signal data : std_logic_vector(7 downto 0) := X"56";
    Eg., reset signal value: 

    
process(clk,rstN)
if (rstN = '0') then
    data <= X"78";
elseif rising_edge(clk) then
   ...
    If you simulate this pair of conditions, and rstN is high at the start of the simulation, then the data value will be X"56". When you assert reset, data will change to X"78".

    The same thing happens in hardware. If your hardware only supports registers that reset to zero, then Quartus will implement not-gate push back, i.e., put inverters on the input and output of the registers to make the register reset zero, but your signal one.

    --- Quote Start ---

    pwm_count <=12; -- integer, is it allow?

    --- Quote End ---

    It depends on what the definition of pwm_count is. If its an unsigned, then sure, no problem. If its an integer, then it would also be ok, however, you'll want to make sure its an integer with a constrained range for synthesis.

    Cheers,

    Dave