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There is something odd among the waveform.
The CONF_DONE raised before the last byte of .rbf was sent.
It's different form the document.
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If you look at figure 1 in the document I linked to, CONF_DONE goes high, and then if you have enabled it, INIT_DONE. If you read the data sheet for the device you are using, there is sometimes a note about sending additional clocks after CONF_DONE goes high, so that the device enters "user mode". Those extra clocks are implemented as extra bytes in the .rbf file, so when you trace configuration of an FPGA, you will see DCLK continue after CONF_DONE asserts. Look at the logic analyzer traces in Figure 31 on p60 - note how the FPGA configuration data bus goes to FFh, but DCLK continues to toggle, and then CONF_DONE asserts. In other devices, it might be that CONF_DONE asserts before DCLK stops toggling. I would not be concerned if that is what you are seeing. The main thing is that if CONF_DONE has asserted, your FPGA is configured correctly.
Cheers,
Dave
Honored Contributor
