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shan039031's avatar
shan039031
Icon for New Contributor rankNew Contributor
4 years ago

Seriallite II protocol and Arria II GX series

Regarding the use of the Seriallite II protocol in hardware: The chip we use is the EP2AGX65DF29C6N of the Arria II GX series. When using quartus II to allocate the pins, it is not clear how the inpu...
CheepinC_altera's avatar
CheepinC_altera
Icon for Regular Contributor rankRegular Contributor
4 years ago

Hi,


Regaring the PCML, as I understand it, it is a standard defined in our transceiver. You may refer to the device datasheet -> "Transceiver Specification" for the specs supported by our transceiver when configured with PCML IO standard.


Regarding your inquiry CML and LVDS, you would need to cross check with the link partners' datasheet to ensure both sides are compatible. For our FPGA, you can check the device datasheet transceiver specification and then compare with 3rd party device's interface requirement/specs. All the transceiver specs need to be compatible.


Regarding your 3rd question on SFP, sorry as I am not familiar with you SFP module. Similar to the above, you would need to ensure the FPGA - SFP modules' interfaces are compatible by checking the interfaces' specs.


Please let me know if there is any concern. Thank you.