New Contributor
Regular ContributorHi,
Thanks for your update. Please see my comments as following:
1. the I/O standard of the rxin signal can be set to LVDS, but the I/O standard of the txout signal cannot be set to LVDS, only 1.4-V PCML, 1.5-V PCML, 2.5V (default) can be set.
[CP] Yes, you are right. If you are using GXB, the TX only support 1.4-V PCML and 1.5-V PCML but no LVDS. You may refer to the device datasheet -> "Transceiver Specifications" for further details
2. whether the rxin and txout signals can only be connected to the GXB bank?
[CP] Yes, they can be connected to GXB bank only.
3. What type of SFP transceiver can be used for 1.5-V PCML？
[CP] It is recommended for you to cross check the transceiver specs in the device datasheet against the SFP modules that you plan to use to ensure they are compatible.
Please let me know if there is any concern. Thank you.
New ContributorThank you for your reply.
Regarding the 1.5V PCML level standard, I only found information about the CML level standard when searching for information. I was a little confused. What is the difference between these two? Is there any information about the PCML level standard?
In addition, I noticed that the main difference between CML and LVDS lies in the voltage swing and data transmission rate. Does SFP that can use LVDS also can use CML?
Finally, there is a question about voltage. SFP is powered by 3.3V. The level standard we use for data transmission on FPGA is 1.5V PCML. Is there any influence between these two voltages? My understanding is that these two are separate and powered by different power sources, so there is no need to consider 3.3V and 1.5V when connecting. Is this understanding correct?
Looking forward to your reply.
