New Contributor
Regular ContributorHi,
Thanks for your update. For your information, the involved IOs seems to range across few types of IOs and it would be rather difficult for me to comment on which pin to use for a specific port.
Just wonder if you plan to port all the IOs of the SLII IP to the FPGA pins?
My recommendation would be for you to let the Fitter perform auto placement for your design if you do not have a specific placement location requirement for now. Generally Fitter will perform the placement for optimal performance provided if you have set the constraints ie SDC constraints upfront. If you encounter any issue along the way, then we could further work out from there.
I am more towards the SLII IP itself and in case you encounter any LVDS IO related problem during the auto-placement, we can further engage the LVDS team to further assist.
Please let me know if there is any concern. Thank you.
New ContributorThank you for your reply.
I have tried to let Fitter perform automatic placement for the design, and set the location according to the setting of the fitter location (pictured), but there is a problem when using LVDS: the I/O standard of the rxin signal can be set to LVDS, but the I/O standard of the txout signal cannot be set to LVDS, only 1.4-V PCML, 1.5-V PCML, 2.5V (default) can be set.
When I tried to connect the txout signal to other banks, the following error occurred:
Error (167081): I/O standard "LVDS" on I/O pin "txout1" is incompatible with the GXB channel's VCCH voltage setting "1.5V"
Error (169004): I/O pin txout1 with Termination logic option setting OCT 100 Ohms cannot be assigned to pin W10 - pin does not support logic option setting
So I want to ask, in the seriallite II IP core,
whether the rxin and txout signals can only be connected to the GXB bank?
Does the txout signal confirm that LVDS cannot be used?
What type of SFP transceiver can be used for 1.5-V PCML？
Another: The FPGA document I refer to is
https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/dp/arria-ii-gx/ep2agx65.pdf
Looking forward to your reply.
