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shan039031's avatar
shan039031
Icon for New Contributor rankNew Contributor
4 years ago

Seriallite II protocol and Arria II GX series

Regarding the use of the Seriallite II protocol in hardware: The chip we use is the EP2AGX65DF29C6N of the Arria II GX series. When using quartus II to allocate the pins, it is not clear how the inpu...
CheepinC_altera's avatar
CheepinC_altera
Icon for Regular Contributor rankRegular Contributor
4 years ago

Hi,


Thanks for your update. For your information, the involved IOs seems to range across few types of IOs and it would be rather difficult for me to comment on which pin to use for a specific port.


Just wonder if you plan to port all the IOs of the SLII IP to the FPGA pins?


My recommendation would be for you to let the Fitter perform auto placement for your design if you do not have a specific placement location requirement for now. Generally Fitter will perform the placement for optimal performance provided if you have set the constraints ie SDC constraints upfront. If you encounter any issue along the way, then we could further work out from there.


I am more towards the SLII IP itself and in case you encounter any LVDS IO related problem during the auto-placement, we can further engage the LVDS team to further assist.


Please let me know if there is any concern. Thank you.