New Contributor
Regular ContributorHi,
As I understand it, you have some inquiries related to the SLII IP. Sorry as I am not very clear with your specific inquiries related to connecting the SLII IP to the FPGA pins. To ensure we are on the same page, would you mind to further elaborate on the specific pin that you are referring to i.e. transceiver pins and etc.
For your information, you may also refer to the example testbench for further details on interconnecting the IPs. You may refer to the SLII IP user guide -> SLII IP Core Testbench section for further details.
Please let me know if there is any concern. Thank you.
New ContributorThank you for your reply.
Regarding the pin connection, the specific problem is this: On the SLII IP, there are data input and output pins, such as rxin, txout, rxrdp_dat[], txrdp_dat[], etc., as well as some other signal pins (with bsf attached).
And on the FPGA chip we use (with pin diagram attached), there are ten banks, of which there are two GXB banks, divided into general purpose I/O, high-speed differential I/O, high-speed differential I/O with DPA, and we also want to use LVDS.
Therefore, we want to find out which bank or IO port these signals on the SLII IP should be connected to, and whether you have any other opinions and suggestions on the use of LVDS in this process.
Looking forward to your reply.
