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Altera_Forum's avatar
Altera_Forum
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15 years ago

serial async transmit

hi all

here is my problem...

i would like to connect range sensor to DE2 kit to show results of the range..

the TX output delivers asynchronous serial with an RS232 format, except voltages are 0-Vcc. The output is an ASCII capital “R”, followed by three ASCII character digits representing the range in inches up to a maximum of

255, followed by a carriage return (ASCII 13). The baud rate is

9600, 8 bits, no parity, with one stop bit

i wrote this code just trying to read the first character "R":

--- Quote Start ---

library ieee;

use ieee.std_logic_1164.all;

use ieee.numeric_std.all;

use work.components.all;

entity sonar is

port ( din,rst : in bit;

clk : std_logic;

data : out bit_vector (7 downto 0);

data_valid : out bit

);

end sonar;

architecture rtl of sonar is

signal sample:std_logic;

signal s:std_logic:='1';

begin

m:sampler port map (clk,sample); // dividing the freq//

process (rst , sample)

variable count: integer range 0 to 10; // start+8 data+stop bits //

variable reg: bit_vector (10 downto 0);

begin

if s<='1' then // to make sure the code will be excuted one time//

if (rst='1') then

count:=0;

reg:=(reg'range =>'0');

data_valid <='0';

elsif (sample'event and sample='1')then

if (reg(0)='0'and din='1')then

reg(0):='1';

elsif (reg(0)<='1') then

count:=count+1;

if (count<10) then

reg(count):= din;

elsif (count=10)then

count:=0;

data_valid <='1';

data<=reg(8 downto 1);

end if;

end if;

end if;

end if;

s<='0';

end process;

end rtl;

--- Quote End ---

and this is my sampler

--- Quote Start ---

library ieee;

use ieee.std_logic_1164.all;

------------------------------

entity sampler is

port (

clk: in std_logic;

sample: out std_logic);

end sampler;

------------------------------

architecture sam of sampler is

begin

process (clk)

variable counter: integer range 0 to 5000:=0;

begin

if (clk'event and clk='1') then

if (counter=5000) then

counter:=0;

end if;

counter:=counter+1;

if (counter>=4999) then

sample<='1';

else sample<='0';

end if;

end if;

end process;

end sam;

--- Quote End ---

and this is my component

--- Quote Start ---

component sampler is

port (clk: in std_logic;

sample: out std_logic);

end component;

--- Quote End ---

after programing i got this result

data='11111111'

could anyone tell me what's wrong?! where is my fault!!

2 Replies

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor

    A UART receiver would be expected to oversample the input and synchronize on a start bit. I can't detect this in your code.

    Using a divided ("ripple") clock has the disadvantage of causing timing conflicts when transfering the UART output to other design parts. The synchronous clock enable method would be preferred.
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor

    --- Quote Start ---

    A UART receiver would be expected to oversample the input and synchronize on a start bit. I can't detect this in your code.

    --- Quote End ---

    what do you suggest?

    --- Quote Start ---

    Using a divided ("ripple") clock has the disadvantage of causing timing conflicts when transfering the UART output to other design parts. The synchronous clock enable method would be preferred.

    --- Quote End ---

    in my code....is there a problem with synchronisation?

    thanx FvM.