victor4
New Contributor
3 years agoSERDES to PCIe4 in Agilex
I am just beginning a design conceptualization where I will use an Agilex FPGA to receive 16-32 lanes of SERDES CML data which has a similarity to XAUI packets including start/stop, sync, error, and 8B/10B encoding bits. All incoming lanes operate at 3.125 Gbps. I have to convert the data to PCIe4x4 because I will be sending it to two Optane P5800X SSDs for storage with a throughput data rate approaching 9GBps. I need to know if the data can be converted and directed into two PCIe buses in real time. I've not used the F-tiles before so I do not know how much latency there is with the conversion nor whether the data conversion can be handled in the fabric without having to be touched by the processor.