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victor4's avatar
victor4
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4 years ago

SERDES to PCIe4 in Agilex

I am just beginning a design conceptualization where I will use an Agilex FPGA to receive 16-32 lanes of SERDES CML data which has a similarity to XAUI packets including start/stop, sync, error, and ...
victor4's avatar
victor4
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4 years ago

Thank you for your reply.

Due to my project schedule and the longer lead time for the Agilex (which supports PCIe4), I may have to use Stratix parts instead. However, Stratix only supports PCIe3. If I have a total data output of almost 9GBps, this will require 3 or 4 PCIe buses to store the data to an SSD drive. Can the data successfully be divided into 4 PCIe3 buses for storage? If so, is this done in the DMA controller?

Harris's avatar
Harris
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4 years ago

Hi Victor,

Every PCIe bus works independently. In theory, the whole throughput can be divided into 4 parallel parts, but it depends on your design. DMA controller only works for data movement, it don't support this division function. Thanks.

BR/Harris