New Contributor
New ContributorHi Victor,
From your description, FPGA should work as PCIe root port mode, and SSD works as EP mode. PCIe system needs to work with software for enumeration, configuration space registers setting, etc. For your case, it is impossible to send data directly to PCIe. You need to use RAM/FIFO to buffer data from Serdes, then design DMA controller to move data from the RAM/FIFO to PCIe endpoint(SSD). Thanks.
BR/Harris
New ContributorThank you for your reply.
Due to my project schedule and the longer lead time for the Agilex (which supports PCIe4), I may have to use Stratix parts instead. However, Stratix only supports PCIe3. If I have a total data output of almost 9GBps, this will require 3 or 4 PCIe buses to store the data to an SSD drive. Can the data successfully be divided into 4 PCIe3 buses for storage? If so, is this done in the DMA controller?
New ContributorHi Victor,
Every PCIe bus works independently. In theory, the whole throughput can be divided into 4 parallel parts, but it depends on your design. DMA controller only works for data movement, it don't support this division function. Thanks.
BR/Harris
