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Altera_Forum
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18 years ago

SERDES in Cylone III

Hi, I am trying to implement a serializer on a Cyclone III EP3C5F256C6. My design is to take 66 LVTTL/LVCMOS inputs and one clock at 133MHz and using a serialization factor of 6, output 11 LVDS...
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Altera_Forum
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17 years ago

I have exactly the same problem! I 'm trying to implement a 48-to-12 ALTLVDS-SERDES circuit for the Cyclone III, that reads data from a RAM memory at CMOS and writes it to a DAC at LVDS. When I use the Vector Waveform Files to simulate my design it makes absolutely no sense to me. Isnt't this SERDERS circuit supposed to function like some kind of multiplexer? pappaloo's post hasn't been answered for about a year. I hope this is not that difficult to figure out! Any help would be appreciated.Thank you