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Altera_Forum's avatar
Altera_Forum
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12 years ago

serailizer/Desserializer solution for Cycole III FPGA

Hi Everyone,

Currently we are designing the project using cyclone III FPGA. Could please help to get info how can i implement serailizer/desserializer in fpga?

here is the my requirement:

TWO SERDES (2 Tx, 2 Rx) on Cyclone 3. With below logic as well

  1. 8b/10b encoding

  2. Data alignment (state machine based sync)TWO SERDES (2 Tx, 2 Rx) on Cyclone 3. With below logic as well

  3. Fifo.

Any help will be highly appreciated.

11 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    12 years ago

    But our customer has decided to use only cyclone III thats why i am asking

  • Altera_Forum's avatar
    Altera_Forum
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    12 years ago

    What's the data speed?

    BTW, you can advice your customer switch to GX.
  • Altera_Forum's avatar
    Altera_Forum
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    12 years ago

    Thanks Jerry for your response!! I came to know from Cyclone III handbook that it has support for same, so we are planing to develop solution in house. BTW can you share information regarding GT, meanwhile your thoughts?

  • Altera_Forum's avatar
    Altera_Forum
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    12 years ago

    --- Quote Start ---

    Thanks Jerry for your response!! I came to know from Cyclone III handbook that it has support for same, so we are planing to develop solution in house. BTW can you share information regarding GT, meanwhile your thoughts?

    --- Quote End ---

    Because you didn't provide the data speed, i don't know if LVDS is ok or not for your case. The CIII family doesn't have GX series device, you can use Cyclone IV GX or Cyclone V GX. The GX series have hard SERDES block inside chip. Altera names this block as GXB.

    If you use LVDS you still can implement SERDES by logic, which is soft SERDES. I remember altera has reference design about this soft serdes, you can contact altera guys to request it.
  • Altera_Forum's avatar
    Altera_Forum
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    12 years ago

    Hi Jerry,

    Yes, we are planning to do use using LVDS. Our target speed is 400 Mbps, is it possible using LVDS in cyclone III?
  • Altera_Forum's avatar
    Altera_Forum
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    12 years ago

    --- Quote Start ---

    Hi Jerry,

    Yes, we are planning to do use using LVDS. Our target speed is 400 Mbps, is it possible using LVDS in cyclone III?

    --- Quote End ---

    It'll be ok even without serdes!
  • Altera_Forum's avatar
    Altera_Forum
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    12 years ago

    Hi Jerry,

    I have one more question for you:-) can i implement USB 2.0 Device function controller in Cyclone V GT/GX? If no then what is the reason? As you know this GT/GX has inbuilt XCVR. Looking forward to your help.
  • Altera_Forum's avatar
    Altera_Forum
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    12 years ago

    --- Quote Start ---

    Hi Jerry,

    I have one more question for you:-) can i implement USB 2.0 Device function controller in Cyclone V GT/GX? If no then what is the reason? As you know this GT/GX has inbuilt XCVR. Looking forward to your help.

    --- Quote End ---

    I didn't implement full USB controller inside FPGA, for our case, we use Cypress's solution. Cypress has USB control chips. You can use these chip outside FPGA, and design control logic inside FPGA.