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Altera_Forum's avatar
Altera_Forum
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10 years ago

Sequential Switching

I am trying to develop a sequencer digital circuit in VHDL and implement it on a DE 1 dev board although I have hit a wall. I have done a signal tap of the output of my FPGA although when I take a lo...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
10 years ago

My experience is the width shown in signaltap does not directly correlate to the actual signal. It is something expected that the TXs' pulses are of same width in your design?

Agree with Daiwen, you should check also if there is any short on the board.