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Altera_Forum
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10 years ago

Sequential Switching

I am trying to develop a sequencer digital circuit in VHDL and implement it on a DE 1 dev board although I have hit a wall. I have done a signal tap of the output of my FPGA although when I take a lo...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
10 years ago

As for the signal I am using for a clock it is the input of my state machine and I will try to check out if there is a short between TX3 and TX4. For now I have attached my VHDL if you can find any errors in here.