Honored ContributorHello everybody!!
I have some doubts about PROCESS and FOR, i want to know how much time spends an instruction inside a process.Also i saw in simulations that instructions inside FOR runs in concurrent mode. How much "sequential" are this two sections of code? Thank you very much Luis
Honored ContributorYou mean PROCESS in VHDL? You might need to explain in more detail what you're looking at. But note that HDL languages are not sequential. In hardware, everything you create runs on every clock cycle, and part of coding is telling it when not to run. It's a very different paradigm that takes a while to get used to, but don't try to write HDL that looks sequential. (For example, stay as far away from variables when starting to code. Most VHDL designers almost never use them, and they generally cause confusion. This is my own opinion, as I have encountered some designers who successfully use them, but they really understand what the synthesis engine is going to do to them and what the final hardware will look like...) Anyway, I may be answering a completely different question so please elaborate on what you're trying to do.
Honored ContributorThe VHDL term sequential designates statements, that are interpreted by the compiler "in in the order in which they appear in the code. VHDL sequential statements can appear only in processes and subprograms." (From Synopsis VHDL Reference Manual). But the logic as a whole is executed fully parallel either permanently (asynchronous) or at a clock edge (sychronous).
The logic generated from sequential code must not necessarily depend on statement order. As Rysc mentioned, this is mainly the case when using variables, that can get multiple assignments (of different values) in a process or subprogram. But in any case, no sequence in time is implied, it's another way to create parallel logic. This could be different in VHDL simulation code, that can use delay instructions to achieve a sequence in time.
