Sequential code vs concurrent code

The VHDL term sequential designates statements, that are interpreted by the compiler "in in the order in which they appear in the code. VHDL sequential statements can appear only in processes and subprograms." (From Synopsis VHDL Reference Manual). But the logic as a whole is executed fully parallel either permanently (asynchronous) or at a clock edge (sychronous).

The logic generated from sequential code must not necessarily depend on statement order. As Rysc mentioned, this is mainly the case when using variables, that can get multiple assignments (of different values) in a process or subprogram. But in any case, no sequence in time is implied, it's another way to create parallel logic.

This could be different in VHDL simulation code, that can use delay instructions to achieve a sequence in time.