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You mean PROCESS in VHDL? You might need to explain in more detail what you're looking at. But note that HDL languages are not sequential. In hardware, everything you create runs on every clock cycle, and part of coding is telling it when not to run. It's a very different paradigm that takes a while to get used to, but don't try to write HDL that looks sequential. (For example, stay as far away from variables when starting to code. Most VHDL designers almost never use them, and they generally cause confusion. This is my own opinion, as I have encountered some designers who successfully use them, but they really understand what the synthesis engine is going to do to them and what the final hardware will look like...) Anyway, I may be answering a completely different question so please elaborate on what you're trying to do.