Send data from FPGA to computer using a USB to TTL

I said write an UART module, means Verilog or VHDL code for it, example below.

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
   
entity TxUnit is
  generic (
      CONSTANT BAUD 	: INTEGER := 26 -- 921 kBaud @ 24 MHz Clk
  );    
  port (
     	Clk    	: in  Std_Logic;  -- Sample CLK
     	Reset  	: in  Std_Logic := '0';  -- Reset input
     	Enable 	: in  Std_Logic := '1';  -- Enable input
     	DataI  	: in	Std_Logic_Vector(7 downto 0); -- Send data
     	TxStrt 	: in 	Std_Logic;  -- Send command
	clkout	: buffer Std_Logic;
	TxRdy  	: out Std_Logic;
     	TxD    	: out Std_Logic);  -- UART data output
end entity;
architecture RTL of TxUnit is
  signal SReg    	: Std_Logic_Vector(7 downto 0); -- Byte send register  
  signal BitPos   : INTEGER range 0 to 11;   -- Position of the bit in the byteframe
  signal clkcount : INTEGER range 0 to BAUD - 1;
begin
	
-- Tx Process
	TxProc : process(Clk,Reset,Enable)
  	begin
     	if Reset = '1' then -- Reset
        	BitPos <= 0;           
 			TxD <= '1';
     	elsif Enable = '1' and Rising_Edge(Clk) then
			if clkcount < BAUD-1 then
				clkcount <= clkcount + 1;
				clkout <= '0';
			else
				clkout <= '1';
				clkcount <= 0;
        	end if;
			case BitPos is
				when 0 =>
					if TxStrt = '1' then -- Start
						BitPos <= 1;
						SReg <= DataI(7 downto 0);
					end if;	
				when 11 => 
					if clkout = '1' then
						BitPos <= 0;
					end if;	
				when others =>
					if clkout = '1' then
						BitPos <= BitPos + 1;
					end if;	
			end case;
			case BitPos is
				when 0 | 1 =>
					TxD <= '1';  -- Idle position
				when 2 =>	
					TxD <= '0';  -- Start bit
				when others =>	
					TxD <= SReg(0); 
					if clkout = '1' then
						SReg <= '1' & SReg(7 downto 1); -- Serialization LSB first
					end if;	
			end case;
     	end if;				-- RisindEdge(clk)
  end process;
  TxRdy <= 	'1' 	WHEN BitPos = 0  ELSE
				'0';
 end RTL;