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- Altera_Forum
Honored Contributor
You need to perform static timing analysis. In addition to that, you can also use gate level simulations.
Quartus has two timing analysis tools: the Classical TA and the TimeQuest TA. TimeQuest is the preferred option, but it does not support old devices. If you're using older devices, such as MAX 3000/7000 CPLDs will have to stick with the Classical TA.