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Altera_Forum's avatar
Altera_Forum
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14 years ago

SDRAM problem in SOPC builder.

Ok.. I realized i posted this in the wrong section of the forum(software), this is probably a hw question, so i repost it here.

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Hi,

I get this warning message in SOPC builder saying:

"Warning: cpu: The address range of the slaves connected to the NIOS 2 instruction master exceeds 28 bits. Attempts to call function across 28 bit boundary is not supported by GCC and will result in linker errors"

when i try to add a SDRAM to my NIOS2 system which already has 128KB on-chip memory, and 2MB SRAM.

But the warning message dissapears after i disconnect the instruction master bus from NIOS2 to the SDRAM. what is the significant of having instruction master bus connected to SDRAM? if i don't connect it, what disadvantage/advantage will i get? the obvious advantage is that, i can generate HDL, since there is no more warning message after disconnecting.

i also found out that, if i define the base memory of SDRAM to be 0x00000000, and SRAM to be 0x0a800000, and lock them both without disconnecting any buses, the warning message will not appear... im confussed..

Someone please answer my question.. i really appreaciate it. Thank you.

regards,

Michael

PS: I'm not a real ALTERA teacher... the forum tries to make fun of me after i asked too much questions here.

1 Reply

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    14 years ago

    Hi Michael

    --- Quote Start ---

    "Warning: cpu: The address range of the slaves connected to the NIOS 2 instruction master exceeds 28 bits. Attempts to call function across 28 bit boundary is not supported by GCC and will result in linker errors"

    --- Quote End ---

    This is because one of the slaves you connected to instruction master has been mapped to address 0x1000 0000 or above.

    Locking base address is the correct procedure. You must have: base_address + slave range < 0x1000 0000

    Connection to instruction master is mandatory if your memory slave is supposed to store code, since Nios use this bus connection to fetch instructions into the cpu for execution.

    If you use a memory device uniquely for data storage, then only connection to data master is required.

    Separate instruction and data paths are convenient because cpu can fetch both an instruction and data in the same cycle, thus increasing performance compared to a single bus machine.

    Regards