SDRAM DQ pin

hi,would you please tell me which pins are assigned to ddr sdram controller,b'se it has lot of pins .is any fixed pins are assigned in fpga for sdram access,please explain(i use cyclone ii(de2))

In that case you don't care about DQ/DQS pins, simply connect you SDR SDRAM to one or several neighbouring banks.

cioma,I use SDR sdram now.

FPGA DQ/DQS designation is for DDRx SDRAM. Do you have DDRx SDRAM or SDR SDRAM?

Okey,ironmoose,thanks for your explanation:-),I still have the question whether it is okey if I use two separated BANK to drive the DQ?

As long as you do not violate the specs of the SDRAM, you should be ok. For example, if you SDRAM VDD is 1.8V, then you should have the FPGA driving pin located in a bank with 1.8V or 1.5V VCCIO. I am assuming these DQ pins will not be used for regular data interface, since you do need to use the FPGA IO pins reserved for DQ/DQS functionality to properly interfae to your DRAM.