Altera_Forum
Honored Contributor
Honored ContributorSDRAM DQ pin
Could anyone tell me whether I can connect the SDRAM DQ pin to FPGA's normal IO not DQS or DQ?What will it happen?
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Altera_ForumHonored Contributor
Honored ContributorAs long as you do not violate the specs of the SDRAM, you should be ok. For example, if you SDRAM VDD is 1.8V, then you should have the FPGA driving pin located in a bank with 1.8V or 1.5V VCCIO. I am assuming these DQ pins will not be used for regular data interface, since you do need to use the FPGA IO pins reserved for DQ/DQS functionality to properly interfae to your DRAM.
