New ContributorHello.
In a custom PCB, I have my SDRAM DQ groups assigned like shown in the photo, with the first DQ group being assigned to DQ[8..16], not DQ[0..7].
Is it required that in order to interface with external SDRAM, my groups start at [0..7]? I suspect this is the case, based on what I read and interpreted in the second screenshot attached, taken from the Cyclone pin description document.
Thanks!
New ContributorNote, however, that my screenshot above says that it must start at [0] for the Hard Memory PHY, but elsewhere in the document when it references just using "external memory," it does not state the same necessity to start at [0]. What is the difference between using the hard memory PHY and just using external memory (SDRAM)?
Super ContributorThe HPS in Cyclone V includes its own hard memory controller as opposed to the soft and hard memory controller options on the FPGA side of the device. Using the HPS hard controller, as you are, is recommended for performance for the HPS. But yes, you should be starting from 0 with it.
New ContributorOkay, thanks. Yes, I am starting from [8] which isn't in accordance with the pin description guide for the Cyclone V HPS hard memory PHY, hence why it is probably not working.
