Sdram_Control_4Port DE2_CCD How the synchronization works ??

Hi,

I'm wondering how does actually frame rate conversion in this example works.

Normally as far as I know one should use at least two frame buffers (ping-pong) to synchronize this.

In this example TRDB-DC2 Cmos sensor gives ~16 Hz (depending on exposure) frames and VGA reads from SDRAM frames at 60 Hz.

Swtiching buffers should be synchronized with the reading VGA. In this case writing a full frame buffer by sensor takes longer than reading a full frame

by VGA so if VGA would switch there would be 'tearing' on the vga output, because VGA would switch buffers in the middle of CMOS sensor write.

To address this issue one should use triple buffering mode and switch output buffer to the one that CMOS just finished writing to and swtich writing the next frame by CMOS to the one not used.

However in this example it seems that there is only one frame buffer. Let's focus on the WR1 and RD1 ports (16 bits), because WR2 and RD2 are simply doing the same just using

different bank of SDRAM memory.

WR1 address is from 0 to 640*512. RD1 reads from 640*16 to 640*496 so its reading from the same address range, simply not using higher 16 and lower 16 lines to cut 512 CMOS lines to 480 VGA lines.

Does anyone knows why is that ?

Sdram_Control_4Port    u6    (    //    HOST Side
                            .REF_CLK(CLOCK_50),
                            .RESET_N(1'b1),
                            //    FIFO Write Side 1
                            .WR1_DATA(    {sCCD_G,
                                         sCCD_B}),
                            .WR1(sCCD_DVAL),
                            .WR1_ADDR(0),
                            .WR1_MAX_ADDR(640*512),
                            .WR1_LENGTH(9'h100),
                            .WR1_LOAD(!DLY_RST_0),
                            .WR1_CLK(CCD_PIXCLK),
                            //    FIFO Write Side 2
                            .WR2_DATA(    {sCCD_G,
                                         sCCD_R}),
                            .WR2(sCCD_DVAL),
                            .WR2_ADDR(22'h100000),
                            .WR2_MAX_ADDR(22'h100000+640*512),
                            .WR2_LENGTH(9'h100),
                            .WR2_LOAD(!DLY_RST_0),
                            .WR2_CLK(CCD_PIXCLK),
                            //    FIFO Read Side 1
                            .RD1_DATA(Read_DATA1),
                            .RD1(Read),
                            .RD1_ADDR(640*16),
                            .RD1_MAX_ADDR(640*496),
                            .RD1_LENGTH(9'h100),
                            .RD1_LOAD(!DLY_RST_0),
                            .RD1_CLK(VGA_CTRL_CLK),
                            //    FIFO Read Side 2
                            .RD2_DATA(Read_DATA2),
                            .RD2(Read),
                            .RD2_ADDR(22'h100000+640*16),
                            .RD2_MAX_ADDR(22'h100000+640*496),
                            .RD2_LENGTH(9'h100),
                            .RD2_LOAD(!DLY_RST_0),
                            .RD2_CLK(VGA_CTRL_CLK),
                            //    SDRAM Side
                            .SA(DRAM_ADDR),
                            .BA({DRAM_BA_1,DRAM_BA_0}),
                            .CS_N(DRAM_CS_N),
                            .CKE(DRAM_CKE),
                            .RAS_N(DRAM_RAS_N),
                            .CAS_N(DRAM_CAS_N),
                            .WE_N(DRAM_WE_N),
                            .DQ(DRAM_DQ),
                            .DQM({DRAM_UDQM,DRAM_LDQM}),
                            .SDR_CLK(DRAM_CLK)    );

Thanks for the reply,

best regards,

madness