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Honored Contributor
Honored ContributorSDRAM Clock
Hi, I use SDRAM controller to connect FPGA and SPANSION(167 MHz) SDRAM. Nios II processor run up to 100 MHZ clock and I can not use higher frequency. I did not use dedicated PLL FPGA pin for S...
Altera_ForumHonored Contributor
Honored ContributorLook at the Embedded IP user guide
https://www.altera.com/content/dam/altera-www/global/en_us/pdfs/literature/ug/ug_embedded_ip.pdf At page 2-10 you'll find the procedure for calculating the optimal sdram clock phase shift.
