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Honored Contributor
Honored ContributorSDRAM Clock
Hi, I use SDRAM controller to connect FPGA and SPANSION(167 MHz) SDRAM. Nios II processor run up to 100 MHZ clock and I can not use higher frequency. I did not use dedicated PLL FPGA pin for S...
Altera_ForumHonored Contributor
Honored ContributorI have seen cases where the SDRAM clock needs to lead nios clock by 3ns assuming Nios is running at 50MHz. Cris did you remember how you characterized the -26 degrees? Is there a formula for SDRAM delay calculation? or trial and error?
