Honored ContributorHi, i use the De2 Altera.
On my board there is Sdram (64 Mbit) I don't understand how can sdram to be 64 mbits. The address pins are 12 (A0-A11) , the banks are 4, the inputs are 16. If i multiplicate 2^12 * 4* 16 i don't have 64 Mbits. Is it possible? I have also CAS and RAS pins...
Honored ContributorSDRam has multiplexed adr lines.
so the full adress is not the address span with pin A0-A11 Thats why CAS and RAS are used CAS means column address strobe RAS means row address strobe for the full memory address, the sdram controler must strobe the column and the row address bits. but CAS width is not the same as RAS width. for example, the Micron MT48LC16M16 SDRam Chip has 1 Chip Select 2 Banks to select upper and lower 8 bit 13 Rows 9 Column 8 Bit per Bank ! (16Bit total due to 2 Banks) That is 2^13 * 2^9 * 16 = 64MBit So have a look at the device and its datasheetHonored ContributorThank you.
I have understood. I have found a vhdl sdram controller on this forum. In this project there is also a vhdl test bench. Do you know if there is a way to use this vhdl test bench in modelsim? Thanks.Honored ContributorSorry, we don't use modelsim as we use Verilog XL on our SUN to simulate
Honored ContributorYou're talking about the 2002 Altera reference design? The test looks pretty like ModelSim.
Honored ContributorHow can i charge the test bench in modelsim?
