Forum Discussion
Altera_Forum
Honored Contributor
7 years agoHi,
The EDA netlist writer does not currently support gate-level simulation for the V-Series Hard IP for PCI Express® MegaCore® Function. https://www.altera.com/support/support-resources/knowledge-base/solutions/rd12102013_720.html Kindly refer previous threads also. https://alteraforum.com/forum/showthread.php?t=36762 https://alteraforum.com/forum/showthread.php?t=50750 Let me know if this has helped or if you need any further assistance. Best Regards, Anand Raj Shankar (This message was posted on behalf of Intel Corporation)