sdo file not generated in altera

Hi,

The EDA netlist writer does not currently support gate-level simulation for the V-Series Hard IP for PCI Express® MegaCore® Function.

https://www.altera.com/support/support-resources/knowledge-base/solutions/rd12102013_720.html

Kindly refer previous threads also.

https://alteraforum.com/forum/showthread.php?t=36762

https://alteraforum.com/forum/showthread.php?t=50750

Let me know if this has helped or if you need any further assistance.

Best Regards,

Anand Raj Shankar

(This message was posted on behalf of Intel Corporation)

Sir,

Thank you very much for the clarity. I have seen the Below things.Let me clear another question Is Timing Quest timing Analysis Possible. If Yes, could you share some procedures to follow the process of Timing Quest timing analysis in same Quartus Prime standard Edition 15.1 version and for the same Cyclone v family devices.

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Hi,

The EDA netlist writer does not currently support gate-level simulation for the V-Series Hard IP for PCI Express® MegaCore® Function.https://www.altera.com/support/support-resources/knowledge-base/solutions/rd12102013_720.html

Kindly refer previous threads also.https://alteraforum.com/forum/showthread.php?t=36762

https://alteraforum.com/forum/showthread.php?t=50750

Let me know if this has helped or if you need any further assistance.

Best Regards,

Anand Raj Shankar

(This message was posted on behalf of Intel Corporation)

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Thanks and Regards

Shyam K