New ContributorSDI pinning on Agilex 5
We are developing a project based on AXE-5 Eagle board and we are facing some issues
We need to drive some clocks and SDI signals through the FMC+ interface, we are defining some pins based in the eagle board user guide. Attached you can find our QSF file.
When we tried to compile we got the following errors, all of them have the same description in the drop down messages.
Initially we thought it could be due to those pins were not assigned to any logic internally, so we tried to set a couple of SDI cores as transmitter and receiver taking as reference the design examples available in the IP parameter editor.
In this case, keeping only the pins connected to any internal logic we got the following errors:
These are signals inside the receiver SDI IP core, we don’t know how to fix this problem.
After facing that issue, we tried to generate the “serial loopback” SDI example, selecting as target development kit “Nextera VIDIO 12G-SDI FMC card” and board ”Agilex 5 I-Series SOC Development kit” in Quartus 24.3.1. Taking this design as base we tried to only modifying some pins to match our needs. In this case we got the following error:
Attached you can find the archived project of the example in case it could be of interest.
At the moment we are stuck on this topic and running out of ideas, we tried with Quartus 24.2.0, 4.3.1 and 25.1 with same results. Maybe we are missing something or doing something wrong.
