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My stupid method is Identify module output the S to external pin, and route this pin back to another pin.
Then use this pin to control Switch module.
The Quartus don't know the relationship between S from external pin and In_a, In_b, the synthesized module can run at 200Mhz.
The key is to disconnect relationship between S and In_a, In_b. The method is using external pin.
But i feel that this method is very stupid.
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I don't understand why you would do this-- S is already internal, and there has to be a known relationship because you know your FPGA clock. Even if that is set using set_false_path, you can build up the timing network.
Honored Contributor
