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hi,
My requriement is that:
There are two input signal, In_a, In_b, these two signals will be connected to clock and data (llike I2C). two output signal, Out_clock, Out_data.
Because the In_a could connect to clock or data, so i need write a module to identify which one(clock or data) will connet to In_a, then re-arrange the order and output the correct signal , i.e. Out_clock or Out_data.
the code is like this:
module Switch(input wire In_a, input wire In_b, input wire S, output wire Out_clock, output wire Out_data)
begin
assign Out_clock = S ? In_a : In_b;
assign Out_data = S ? In_b : In_a;
end.
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Someone else might have a better idea, but I'd treat both signals as tied to a virtual 100 MHz clock and use that in the set_input_delay for both of the signals. The question is where the first latch is going to be, and how you want to register these signals. set_input_delay can create the relationship between the virtual clock and the FPGA-based clock, but as of now you have two signals that are unregistered.
Maybe consider a fast_input_register setup on each of them latched to the FPGA clock before doing anything else to them to get known signal timing?
Also, if one of these clocks is actually going to be used as a clock, that means the out_clock should be in the SDC as a virtual clock in the system.
Hopefully others with more experience can provide some better resources.
Honored Contributor
