Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

SDC problem

Hi, i want to implement a SoC with the maximum frequency of my board StratixIV Gx. I used one pll with two output, first output pll.c0=150Mhz, second output is 125Mhz. After a compilation and...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

--- Quote Start ---

Yes there are 131,072Kb implemented at this adress. it start by 00040000 and finished by 0005ffff.

--- Quote End ---

So what clock is used by the NIOS processor and to access that memory?

What does the TimeQuest timing report indicate for that data path, or for the clock domain used by the processor and memory?

Cheers,

Dave