Forum Discussion
Altera_Forum
Honored Contributor
Honored ContributorSDC problem
Hi, i want to implement a SoC with the maximum frequency of my board StratixIV Gx. I used one pll with two output, first output pll.c0=150Mhz, second output is 125Mhz. After a compilation and...
Altera_ForumHonored Contributor
Honored Contributor --- Quote Start --- So what is at that address? On-chip memory, external memory? Do you know that memory works correctly? If you are serious about doing FPGA development, then you need to learn to use all the tools. Modelsim is very useful for confirming that your system works, before you try to debug in hardware. Cheers, Dave --- Quote End --- The address corresponds to on chip memory. I use just on-chip memory on my design. For the memory worked correctly.
