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Altera_Forum's avatar
Altera_Forum
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14 years ago

SDC problem

Hi, i want to implement a SoC with the maximum frequency of my board StratixIV Gx. I used one pll with two output, first output pll.c0=150Mhz, second output is 125Mhz. After a compilation and...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
14 years ago

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This the error message that appears on console

verifying 00040000 ( 0%)

verify failed between address 0x40000 and 0x4655f

leaving target processor paused

also it appear a window that contain problem occured downloading elf process failed.

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So what is at that address? On-chip memory, external memory? Do you know that memory works correctly?

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I don't try to use a modelsim, because i don't know how can i use with nios-eclipse.

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If you are serious about doing FPGA development, then you need to learn to use all the tools. Modelsim is very useful for confirming that your system works, before you try to debug in hardware.

Cheers,

Dave