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Altera_Forum's avatar
Altera_Forum
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15 years ago

SDC problem

Hi, i want to implement a SoC with the maximum frequency of my board StratixIV Gx. I used one pll with two output, first output pll.c0=150Mhz, second output is 125Mhz. After a compilation and...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

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You can only resolve it by understanding it.

'Nothing works' is too vague. If you said something like "Accesses to an Avalon-MM slave at address XXX from C code running on a NIOS II processor, causes the processor to lock-up (no communications) ..." that would be a little more specific.

If you have two clocks in the system, then I you must have clock-domain crossing logic in the system to ensure valid data transfers.

Have you tried simulating your design in Modelsim?

Cheers,

Dave

--- Quote End ---

Thank you for your reply

Sorry, since i don't explain the problem exactly. This the error message that appears on console

verifying 00040000 ( 0%)

verify failed between address 0x40000 and 0x4655f

leaving target processor paused

also it appear a window that contain problem occured downloading elf process failed.

I don't try to use a modelsim, because i don't know how can i use with nios-eclipse.