SDC problem

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i want to implement a SoC with the maximum frequency of my board StratixIV Gx.

I used one pll with two output, first output pll.c0=150Mhz, second output is 125Mhz. After a compilation and download the program to the board, and try to execute my C code, nothing that work.

When i use the same output clock, it work correctly.

How can i resolve this problem.

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You can only resolve it by understanding it.

'Nothing works' is too vague. If you said something like "Accesses to an Avalon-MM slave at address XXX from C code running on a NIOS II processor, causes the processor to lock-up (no communications) ..." that would be a little more specific.

If you have two clocks in the system, then I you must have clock-domain crossing logic in the system to ensure valid data transfers.

Have you tried simulating your design in Modelsim?

Cheers,

Dave