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Vic3Dexe
Occasional Contributor
Occasional ContributorSDC constrains for async static RAM
I have async static RAM with 10 ns access time.
I try to read data from it in such a way, that address formed in one register, then data latched to another, both have the same clock 50 MHz (20 ns)....
Vic3DexeOccasional Contributor
Occasional ContributorWell, it seems to me I've forced it to work.
I've assigned ADDR pins to fast output, and DATA pins to fast input/output.
Then, I've created a new clock with PLL, it's the same 50 MHz, but with 90 degree shift. With this clock I've moved the nWR pulse a little forward.
Idk what have actually helped - the fast registers thing or shifted clock, but for now I can't reproduce any errors.
One thing I can't figure out: why signaltap don't show me the phase shift?
Here is the screenshot, capture on 200 MHz from PLL, trigger on falling edge of nWR.
add: seems it is shifted clock. I've tried to switch nWR back to the 0 degree one, and got errors.
