SDC constrains for async static RAM

Well, it seems to me I've forced it to work.

I've assigned ADDR pins to fast output, and DATA pins to fast input/output.

Then, I've created a new clock with PLL, it's the same 50 MHz, but with 90 degree shift. With this clock I've moved the nWR pulse a little forward.

Idk what have actually helped - the fast registers thing or shifted clock, but for now I can't reproduce any errors.

One thing I can't figure out: why signaltap don't show me the phase shift?

Here is the screenshot, capture on 200 MHz from PLL, trigger on falling edge of nWR.

add: seems it is shifted clock. I've tried to switch nWR back to the 0 degree one, and got errors.