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Vic3Dexe's avatar
Vic3Dexe
Icon for Occasional Contributor rankOccasional Contributor
3 years ago

SDC constrains for async static RAM

I have async static RAM with 10 ns access time. I try to read data from it in such a way, that address formed in one register, then data latched to another, both have the same clock 50 MHz (20 ns)....
Vic3Dexe's avatar
Vic3Dexe
Icon for Occasional Contributor rankOccasional Contributor
3 years ago

2Nurina

I'm really appreciate for help.

1. Logic lock is overkill. It should work without such a deep intervetion. It's a simple RAM, come on!

2. I've found some logic between data/addr register and FPGA ports. Totally forgot about that. So I've removed this logic (strictly speaking, I've moved it behind registers), and now reading is perfect. I've even removed set_max_delay lines in SDC. This is good, because I don't understand what they did anyway )

3. But then a new problem arrived: in some cases write is failing, and I don't understand why. Maybe again it is logic on the nWR line, idk. I can't remove this logic right now, will try some workaround.

4. About this topic... I've asked about constrains for static RAM, delays is a secondary problem, it should be resolved by correct SDC. I'm now reading this, it is much more close to what I need. Hope it will help. If you want to close this topic - it's ok.

ps One more question: are there any major differences between Cyclone III and IV?

I mean, i/o buffers or smth. Because I did something similar couple years ago on Cyclone IV, and have no problems at all without any constrains, fast registers etc.