SDC constrains for async static RAM

In your example you have md assigned twice, is it ok?

    assign 		md = mr & mrd ? mdo : {12{1'bz}};
...
    assign 		md = mr & ~mw & enb_ext ? ext_dq : {12{1'bz}};

And mdo is actually read from internal memory, not external

   always @(posedge clk)
	begin
        if (mwr) memory[addr] <= #TPD mdi;
        mdo <= #TPD memory[addr];
	end

while data from external (as far as I understand) is not registered, md lines are just output of the module

   assign 		ext_dq = mw & ~mr ? mdi : {12{1'bz}};
    assign 		md = mr & ~mw & enb_ext ? ext_dq : {12{1'bz}};

So it's not my case, my problem starts when I try to register md lines.

And in these lines

set_input_delay -clock CPUCLK -max 10.0 [get_ports {SRAM_DQ[*]}]
set_input_delay -clock CPUCLK -min  3.0 [get_ports {SRAM_DQ[*]}]
set_multicycle_path -from [get_ports {SRAM_DQ[*]}] -rise_to CPUCLK -setup 2
set_multicycle_path -from [get_ports {SRAM_DQ[*]}] -rise_to CPUCLK -hold 2

10 and 3 are what? Ok, lets assume 10 is 10 ns access time. So what is 3? Hold time? Why 3? Shouldn't it be negative?

Multicycle is 2... why? In your code you set address at negedge and latch data at posedge (lets assume you read external RAM). Isn't it all counts as only 1 cycle?

Same in these lines

set_output_delay -clock CPUCLK -clock_fall -max 4.0 [get_ports {SRAM_*_L SRAM_A[*]}]
set_output_delay -clock CPUCLK -clock_fall -min 0.5 [get_ports {SRAM_*_L SRAM_A[*]}]

where 4 and 0.5 comes from?

I appreciate for helping, but I want not only copy-paste, I want to understand what I copypasting )