Dear Tricky, you can name it a gap in knowledge , may be , because I had implemented many circuits before as SDHC, wavelet and VGA... I show the error in this code because it was the same when I used the SRAM in code below .
IF (wr_done='0') THEN
wr_enable := clk;
test <= D(7 DOWNTO 0);
A <= std_logic_vector(to_unsigned(i,18));
ELSE
test <= D(7 DOWNTO 0);
A <= std_logic_vector(to_unsigned(vac,18));
wr_enable := '1';
END IF;
nWE <= wr_enable;
wdone_test <= wr_enable;
--Bidirectional bus:--------------
IF (wr_enable='0') THEN
D <= "00000000" & myram(i);
ELSE
D <= (OTHERS => 'Z');
END IF;
END PROCESS;
END ARCHITECTURE;
here when I replaced myram with SD data I got the same error. And the code above worked well with VGA and images are shown correctly and the ram is created. If I had a problem with basics it wouldn't run eventually. However if you think it is a basic question , I wish you guide me to what to read to pass it.
Thank you
With my best regards.